Intel and Micron reveals 3D Xpoint a new way to store data that they say is denser, tougher, and faster than the competition, and it's already starting production.

In a live keynote today, the companies announced 3D Xpoint, a new category of non-volatile memory that claims to be 1,000 times faster than the NAND architecture underlying most flash memory cards and solid state drives.

According to The Verge, the new architecture does without transistors entirely, relying on a bulk material property change to switch bits from a low-resistance to a high-resistance state.

From there, memory cells are layered in an intricate three-dimensional checkerboard pattern that Intel researchers say is 10 times denser than conventional memory.

"For decades, the industry has searched for ways to reduce the lag time between the processor and data to allow much faster analysis," said Intel VP Rob Crooke in a statement.

"This new class of non-volatile memory achieves this goal and brings game-changing performance to memory and storage solutions."

The limitations of the new memory class are still unclear, but its earliest applications are likely to be in real-time data analysis, where fast access to large datasets is at a premium. Intel singled out fraud detection and disease tracking as likely early applications, but said the chip could also be used to power more immersive gaming experiences if brought to the PC.

Because the memory is durable and non-volatile, it's likely to be used primarily for long-term storage, but executives at the keynote said fast access to that long-term data could enable entirely new applications for everyday services.

Intel and Micron aren't revealing some technology details of 3D Xpoint, including key materials they are using. But they described what they said is a unique way to store data, using vertical columns of circuitry linked by a crisscross grid of microscopic wires, WSJ reported.

Among other things, the approach allows cells that store data to be managed individually; NAND flash chips require entire blocks of cells to be erased before a single bit is stored, slowing performance.

"This is something many people thought was impossible," said Crooke.

The companies initially planned to manufacture two-layer chips that store 128 gigabits of data, matching some existing NAND chips. They plan to boost capacities later by stacking more circuitry.